1. Field of the Invention
The present invention relates in general to integrated circuit (IC) manufacture, and more particularly to improving patterning accuracy and minimization of line-width variations in the optical patterning process used to print a pattern on a photoresist layer on a semiconductor wafer.
2. Description of Related Art
Manufacture of integrated circuit devices involves repeated sequences of the steps of deposition, photolithographic patterning, and etching. During deposition, a layer of conductive or insulating material is deposited on the surface of a silicon wafer. This material is then coated with a photosensitive resist. During the step of photolithographic patterning, which includes a set of optical and chemical processes, images of some desired geometric patterns residing on a photomask (also referred to as a “reticle” or simply “mask”) are transferred onto the photo resist. The wafer is then developed and etched to remove material from the areas exposed to light, corresponding to clear areas in the photomask images. This is illustrated in FIG. 1. The sequence is repeated a number of times to implement the desired circuit structures.
The primary tool used for projecting a circuit image from a photomask onto a resist-coated wafer is the wafer stepper. They are generally of two kinds: a “step-and-repeat” type and a “step-and-scan” type. In both cases the photomask or reticle generally contains multiple copies of the master image of a chip layout design, and the exposure is performed at an entire “reticle field” level, as illustrated in FIG. 2. In some instances, a single photomask may also consist of layouts for multiple devices, a practice quite frequent in foundries.
Advances in the patterning technologies have enabled the printing of ever-smaller features onto a silicon wafer. The resolution of a lithographic process refers to its ability to separate component parts of an image, as measured by the smallest feature size or Critical Dimension (CD) that is printable with the given process. The CD is a function of three parameters:CD=k1(λ/NA)where λ is the wavelength of the exposure light, NA is the numerical aperture of the projection system, and k1 is a process-related factor that serves as a measure of the degree of “difficulty” of the lithographic process.
Continuing minimum CD reduction and tighter CD uniformity control are of paramount importance in the manufacture of integrated circuits. They allow device manufacturers to produce smaller, faster, and lower power products at ever-lower costs. The reduction in CD is achieved by decreasing λ, increasing NA, or decreasing k1. The reduction in λ follows a step function, going from 365 nm, to 248 nm, to the current state-of-the-art 193 nm, where each step typically lasts 5˜8 years. Current state-of-the-art 90 nm IC manufacturing process has a printable CD on the order of around 50˜60 nm. But as the CD drops below the illumination wavelength, the image quality degrades rapidly due to diffraction and other effects. Pattern sizes become increasingly sensitive to the characteristics of the patterning tools and fluctuations in the manufacturing process.
In order to achieve superior patterning, a number of resolution enhancement techniques (RET) have been developed over time. Such RET's have now become a part of the IC design-manufacturing flow. Examples of current RET's include optical proximity corrections (OPC), off-axis illumination (OAI), phase-shift masks (PSM), and tiling. The practice of these prior art RET techniques follows a process flow shown in FIG. 3.
The challenge in patterning at deep sub-wavelength feature sizes stems from the fact that image patterns as printed on the wafer get distorted from the original intended patterns, as illustrated in FIG. 4. An example of such image shape distortions is line shortening, whereby the length of a printed line is less than its intended nominal length. Another form of image distortion is corner rounding, where an intended sharp corner turns into a rounded one. Yet another type of image distortion is the so-called iso-dense effect, whereby lines print thinner when they are isolated (i.e., by themselves) than if they were amidst other patterns. Further, the part of a line emerging from a cluster of patterns often prints thinner than other parts of the same line within the cluster of patterns. Other factors that cause the same nominal line width to print differently include environmental variations, developer induced effects, and etch effects.
RET's, especially OPC techniques, attempt to compensate for patterning process aberrations and variabilities to achieve better patterning accuracy and CD uniformity control. Some of these prior art techniques are illustrated in FIG. 5. For years, IC manufacturers have compensated isolated lines by making them wider (called iso-dense biasing). More recently, a variety of optical proximity corrections (OPC) have been brought into practice. The simplest OPC examples attempt to offset the loss of high frequencies or counter the effects of diffraction and/or scattering by appending the intended layout features with sub-resolution assist features or SRAF's such as serifs, hammerheads, corner cutouts, and scattering bars. These SRAF's do not actually print on the wafer, but generate the appropriate optical behavior that results in the intended features to print right. These techniques worked adequately, for example, at the 0.25 μm technology node.
At even smaller feature sizes (e.g., 0.18 μm), more sophisticated OPC techniques were necessary to compensate for pitch-sensitivity of patterns and diffraction effects. The two most common techniques are model-based OPC (MOPC) and rule-based OPC (ROPC), as illustrated in FIG. 6. In MOPC, the patterning process is modeled and simulated, based on which the likely printed pattern is predicted. Based on this, the layout is modified, and the simulation is performed again. This iterative process is repeated until the predicted pattern converges to the intended layout pattern. The difficulty with this approach is that it is iterative in nature and takes long computation times.
In ROPC, rather than rely on modeling and simulation, empirical data is obtained by measuring the actual results from the patterning process, and the appropriate mask CD required to produce a desired target wafer CD are determined. Once such “look up tables” are generated for a range of process conditions, the layout features on the mask are heuristically pre-compensated in order to achieve the target results on the wafer.
While these prior art techniques improve the patterning accuracy and CD uniformity, CD variations today remain intolerably high, both within an IC chip and across a stepper field, and will become increasingly more problematic at 0.13 μm and finer feature sizes. These CD variations are broadly categorized as across the chip line-width variabilities (ACLV) and across the reticle field line-width variabilities (AFLV). As the lithographic process advances from 248-nm to 193-nm stepper technologies and beyond, ACLV/AFLV problems will continue to get worse. Significant portions of these variabilities are as a result of systematic variabilities from the patterning process itself, which includes both the process steps, and the tools that are used in each step (e.g., mask writer, stepper/scanner, etcher, chemical-mechanical polishing (CMP) equipment).
One of the reasons the prior art techniques still leave a sizable portion of the image distortions uncorrected is that they assume that these distortions are fixed across the entire chip as well as the stepper field. This assumption is in fact far from reality. Furthermore, they are designed for general applicability and do not take into account the specific tools- or process-induced aberrations and their unique variability signatures. As illustrated in FIG. 6, the actual behavior of the physical tools and processes is reflected by linewidth variations across a reticle field, which is not effectively dealt with by prior art RET. In MOPC, the modeling does not adequately factor the within-field variations. In ROPC, the mask CD selected to produce a target wafer CD is not a constant number that can work for all field locations.
Therefore, what is needed is a correction method that is performed on a location specific, reticle-wide scale, for a specific tools/process combination, such that, e.g., distortions that are unique to a particular tools/process and are reticle-field-location dependent due to projection lens aberrations, can be fully compensated for.
Furthermore, vendors sell optical proximity correction software to manufacturers of semiconductor devices. Manufacturers are responsible for the increasingly-complex task of obtaining necessary characterization data to calibrate their optical proximity correction models and using such models on these software tools to correct customers' IC layout to account for proximity effects. Regardless of the scope of implementing OPC corrections, may it be for the 180 and 130 nm generations or prior generations or more state-of-the-art 90 and sub-90 nm generations, OPC and RET implementation is a very time-consuming process, and IC manufacturers are looking for more effective and efficient solutions.